module rst_gen(
    input arst_n,
    input sys_clk,
    output rst_n
);
    reg rst_sync0;
    reg rst_sync1;

    always @(posedge sys_clk, negedge arst_n) begin
        if (~arst_n) begin
            rst_sync0 <= 1'b0;
            rst_sync1 <= 1'b0;
        end else begin
            {rst_sync1, rst_sync0} <= {rst_sync0, 1'b1};
        end
    end
    assign rst_n = rst_sync1;

endmodule
